libpfm_intel_spr(3) — Linux manual page

NAME \| SYNOPSIS \| DESCRIPTION \| MODIFIERS \| OFFCORE_RESPONSE events \| AUTHORS \| COLOPHON

LIBPFM(3)               Linux Programmer's Manual              LIBPFM(3)

NAME top

       libpfm_intel_spr - support for Intel SapphireRapid core PMU

SYNOPSIS top

       #include <perfmon/pfmlib.h>

       PMU name: spr
       PMU desc: Intel SapphireRapid

DESCRIPTION top

       The library supports the Intel SapphireRapid core PMU. It should
       be noted that this PMU model only covers each core's PMU and not
       the socket level PMU.

       On SapphireRapid, the number of generic counters depends on the
       Hyperthreading (HT) mode.

       The pfm_get_pmu_info() function returns the maximum number of
       generic counters in num_cntrs.

MODIFIERS top

       The following modifiers are supported on Intel SapphireRapid
       processors:

       u      Measure at user level which includes privilege levels 1,
              2, 3. This corresponds to PFM_PLM3.  This is a boolean
              modifier.

       k      Measure at kernel level which includes privilege level 0.
              This corresponds to PFM_PLM0.  This is a boolean modifier.

       i      Invert the meaning of the event. The counter will now
              count cycles in which the event is not occurring. This is
              a boolean modifier

       e      Enable edge detection, i.e., count only when there is a
              state transition from no occurrence of the event to at
              least one occurrence. This modifier must be combined with
              a counter mask modifier (m) with a value greater or equal
              to one.  This is a boolean modifier.

       c      Set the counter mask value. The mask acts as a threshold.
              The counter will count the number of cycles in which the
              number of occurrences of the event is greater or equal to
              the threshold. This is an integer modifier with values in
              the range [0:255].

       ldlat  Pass a latency threshold to the
              MEM_TRANS_RETIRED:LOAD_LATENCY event.  This is an integer
              attribute that must be in the range [1:65535]. It is
              required for this event.  Note that the event must be used
              with precise sampling (PEBS).

       intx   Monitor the event only when executing inside a
              transactional memory region (in tx). Event does not count
              otherwise. This is a boolean modifiers. Default value is
              0.

       intxcp Do not count occurrences of the event when they are inside
              an aborted transactional memory region. This is a boolean
              modifier. Default value is 0.

       fe_thres
              This modifier is for the FRONTEND_RETIRED event only. It
              defines the period in core cycles after which the
              IDQ_*_BUBBLES umask counts. It acts as a threshold, i.e.,
              at least a period of N core cycles where the frontend did
              not deliver X uops. It can only be used with the
              IDQ_*_BUBBLES umasks. If not specified, the default
              threshold value is 1 cycle. the valid values are in
              [1-4095].

OFFCORE_RESPONSE events top

       Intel SapphireRapid supports two encodings for offcore_response
       events. In the library, these are called OFFCORE_RESPONSE_0 and
       OFFCORE_RESPONSE_1.

       Those events need special treatment in the performance monitoring
       infrastructure because each event uses an extra register to store
       some settings. Thus, in case multiple offcore_response events are
       monitored simultaneously, the operating system needs to manage
       the sharing of that extra register.

       The offcore_response events are exposed as a normal events by the
       library. The extra settings are exposed as regular umasks. The
       library takes care of encoding the events according to the
       underlying kernel interface.

       On Intel SapphireRapid unlike older processors, the event is
       treated as a regular event with a flat set of umasks to choose
       from.  It is not possible to combine the various requests,
       supplier, snoop bits anymore. Therefore the library offers the
       list of validated combinations as per Intel's official event
       list.

AUTHORS top

       Stephane Eranian <eranian@gmail.com>

COLOPHON top

       This page is part of the perfmon2 (a performance monitoring
       library) project.  Information about the project can be found at
       ⟨http://perfmon2.sourceforge.net/⟩.  If you have a bug report for
       this manual page, send it to
       perfmon2-devel@lists.sourceforge.net.  This page was obtained
       from the project's upstream Git repository
       ⟨git://git.code.sf.net/p/perfmon2/libpfm4 perfmon2-libpfm4⟩ on
       2024-06-14.  (At that time, the date of the most recent commit
       that was found in the repository was 2024-04-24.)  If you
       discover any rendering problems in this HTML version of the page,
       or you believe there is a better or more up-to-date source for
       the page, or you have corrections or improvements to the
       information in this COLOPHON (which is not part of the original
       manual page), send a mail to man-pages@man7.org

                               April, 2022                     LIBPFM(3)